Theory of operation

The block diagram below illustrates the main functional blocks of the SARK-110 Antenna Analyzer:



The SARK-110 comprises four main sections: a signal generator used as an active source, a bridge to provide signal separation, two tuned receivers that downconvert and detect the signals and a microcontroller and display for calculating and reviewing the results.

The signal generator is provided by a single chip dual direct digital synthesizer (DDS) AD9958 from Analog Devices, which generates a sinusoidal signal for impedance measurement and a local oscillator signal for the tuned receivers (mixers).  One of the DDS channels operates at the specified test frequency and the other is programmed to operate just 1 kHz above it, which is the value of the intermediate frequency. The DDS has an internal oscillator driven by an external 24 MHz crystal and is able to multiply this clock internally by a user configurable factor of 4 to 20, so the maximum internal clock frequency is 480 MHz. In general the DDS can be configured to generate a frequency of up to one third of the clock frequency but in this design, due to the external reconstruction filter, it is possible to achieve an output frequency of up to 230 MHz.

The amplitude level of the DDS channel’s output is frequency dependent and it is reduced with increasing frequency following a SIN(X)/X function. The SARK-110 software compensates for this amplitude rolloff effect by using the capability of the DDS to adjust the amplitude level of the output signal, so the analyzer maintains a flat output amplitude.

The output of each of the DDS channels is differential and is amplified by a dual high speed current feedback amplifier working in differential input mode and with output in single ended mode. Most DDS designs use a broadband balun transformer to convert to single end mode but because of the restricted height available in the SARK110 enclosure a silicon-based solution was chosen.

The output of each amplifier is followed by elliptic low pass filters with a cut-off frequency of 230 MHz. These filters reduce the level of spurious high frequency components that appear in the output of the DDS. These high frequency components consist of aliases at multiples of the internal clock frequency as well as other spurs. 
For impedance measurement a resistive bridge is used because of its simplicity and good frequency response, working down to DC. In the bridge a voltage across one resistor is proportional to the voltage being applied to the circuit under test and the voltage across another resistor is proportional to the current flowing into the circuit connected to the analyzer’s test port. Both the magnitude and phase are measured. The ratio of the two corresponds to the impedance we want to measure.

One of the mixers is used for the voltage measurement and the other for the current measurement. The output of the mixers is the 1 kHz I.F. signal which is then amplified and filtered with a bandpass filter before digitizing. Identical mixer and amplifier circuits are used for both the voltage and current sensing paths. Any small differences in the gain and phase shift of these two signal paths are taken care of by the calibration process.

The core of the analyzer is an STM32F103 microcontroller from STMicroelectronics. This microcontroller incorporates the high-performance ARM Cortex M3 32 bit core operating at 72 MHz, a Flash memory of 256 KB, SRAM of 48 KB, and an extensive range of I/O and peripherals including a USB device controller and three 12-bit ADC converters. The digitizing of the 1 KHz I.F. signal is done by two independent 12-bit ADC converters contained in the STM32 MCU. These two converters operate simultaneously and are synchronized, so providing good accuracy for the phase measurement.

The two sets of digital data from the voltage and current sensors are analyzed using an optimized implementation of the discrete Fourier transform that works with a single bin. This produces the amplitude and phase of the 1 kHz fundamental signal and cancels out any dc component due to offsets in the operational amplifiers. The load impedance magnitude is the voltage amplitude divided by the current amplitude. The phase angle of the impedance is the difference in the phase angles of the voltage and current. Knowing these two parameters, we can calculate the equivalent resistance and reactance of the load impedance. The rest of the parameters such as VSWR, reflection coefficient, etc. are derived from the measured impedance value.